Domino Logic

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Brief Description: The invention offers a high speed, low power domino logic circuit for microprocessors. The design involves a dynamic body biased keeper circuit which simultaneously reduces power consumption and enhances speed.. Applications: For CMOS logic circuits requiring high speed. Advantages: Domino CMOS logic circuits which are commonly used in high performance microprocessors for their high speed and area characteristics, are highly sensitive to noise as compared to static gates. In standard domino logic gates, a feedback keeper is employed to maintain the state of the dynamic node against coupling noise, charge sharing, and threshold leakage current. The contention between the keeper and the pull down network transistors degrades the circuit speed and power characteristics. Modifications previously proposed to reduce the contention current have been unreliable in increasingly noisy and noise sensitive on-chip environment. In the proposed domino logic structure, the threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without degrading the noise immunity. Such a structure is shown to have speed enhancement of up to 66% while reducing power dissipation by 43% as compared to standard domino logic circuits.